DFT Architect

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

•       Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

•       Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

•       IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

•       If you have an idea, we test it. If it works, we ship it.

•       No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

•       US team: Bay Area preferred, but we hire the best people regardless of location

•       India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

•       Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.

•       Bias for action. We move fast. Analysis paralysis doesn't fly here.

•       Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.

•       Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

•       The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

•       The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.

•       The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.

•       The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

About the role

We are looking for an experienced DFT Architect to lead Design-for-Test strategy, architecture definition, and implementation for complex ASIC/SOC designs across advanced technology nodes. The ideal candidate will drive end-to-end DFT architecture including scan, MBIST, compression, boundary scan, and at-speed test methodologies while collaborating with cross-functional teams to achieve high test coverage, quality, and silicon bring-up success.

What you'll do

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs. 

• Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies. 

• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals. 

• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff. 

• Analyze and resolve DFT-related timing, routing, and testability challenges. 

• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization. 

• Develop and enhance DFT automation flows, methodologies, and reusable infrastructure. 

• Mentor junior engineers and provide technical leadership across projects. 

What We’re Looking For 

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. 

• 10+ years of experience in ASIC/SOC DFT implementation and architecture. 

• Strong expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT methodologies. 

• Hands-on experience with industry-standard DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent. 

• Strong understanding of RTL design, timing, physical design constraints, and silicon debug. 

• Experience with advanced technology nodes and large SOC integration. 

• Strong scripting and automation skills using Tcl, Python, Perl, or Shell. 

• Excellent leadership, problem-solving, and cross-functional collaboration skills. 

Good to Have 

• Experience with automotive safety standards such as ISO 26262. 

• Exposure to chiplet-based architectures and 3D IC testing methodologies. 

• Knowledge of diagnosis-driven yield improvement and silicon analytics. 

Success in This Role Looks Like 

• Delivery of robust DFT architectures with high test coverage and efficient manufacturing test cost. 

• Successful silicon bring-up with minimal DFT-related issues. 

• Improved DFT methodology scalability, automation, and execution efficiency. 

• Strong technical leadership and contribution to organization-wide DFT best practices.