SystemVerilog/UVM Design Verification Engineer

Job Description:

• The Verification Engineer will contribute to the pre-silicon functional verification of high-performance SoCs and related subsystems.
• This role requires a senior-level verification engineer who can work independently and take ownership of verification deliverables within a UVM/SystemVerilog environment.
• The engineer will collaborate with design, architecture, and validation teams to ensure thorough functional and coverage verification prior to tape-out.

Responsibilities:

• Perform pre-silicon functional verification of digital designs using UVM and SystemVerilog methodologies.
• Develop, enhance, and maintain UVM-based testbenches, sequences, and scoreboards for block and system-level verification.
• Write and execute constrained-random and directed testcases; implement coverage models and assertions to ensure design quality and completeness.
• Debug functional and simulation issues, analyze waveform results, and collaborate closely with design engineers to identify and resolve root causes.
• Validate PCIe, AXI, and SoC interfaces for performance, compliance, and integration.
• Apply intermediate-level Python scripting to automate regression runs, data analysis, and verification flows.
• Maintain and update verification matrices, test plans, and coverage reports to track progress toward sign-off.
• Work independently within an established verification framework, ensuring high-quality and on-time delivery of all assigned verification tasks.

Experience:

• 5–8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC).
• Strong proficiency in SystemVerilog and UVM (must be able to work independently).
• Experience with functional and code coverage closure, assertion-based verification, and debugging complex designs.
• Hands-on experience with PCIe, AXI4, and processor/SoC-related flows.
• Solid understanding of simulation environments and regression debugging using tools like Questa, VCS, or Xcelium.
• Working knowledge of Python (intermediate scripting) — must be able to automate test or regression flows

Skills:

• UVM/System Verilog
• Design Verification
• Ethernet, SPI, AXI, JTAG
• SDF and GLS simulations
• Python

Education:

• Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.