Principal SoC I/O Performance Architect

THE ROLE

AMD is seeking a Principal I/O Performance Architect to help define and optimize I/O performance across next-generation SoCs—before the silicon exists and after it returns from the fab. You'll define what 'fast enough' means for bandwidth, latency, and QoS, build the models and experiments that prove it, and use that evidence to steer architecture and design decisions across the company. 

This is a rare seat at the intersection of architecture, modeling, verification, emulation, firmware/software, and post-silicon analysis. You won't just run tools and report numbers—you'll frame the questions, build the evidence, and drive the decisions. This role offers a unique opportunity to shape the performance strategy of cutting-edge AMD technologies from early concepts through silicon and into platforms. 

THE PERSON

You are a systems thinker who combines architecture judgment, modeling discipline, and post-silicon grounding to help teams make better decisions earlier. You reason from data, build the evidence yourself, and turn complex system behavior into clear recommendations that engineers actually act on. Your background may be in SoC or I/O architecture, performance modeling, DV or performance verification, emulation, firmware/software performance, or post-silicon validation—what matters most is that you understand how complex systems interact, influence across boundaries, and drive decisions through evidence rather than authority. 

KEY RESPONSIBILITIES 

• Define performance objectives, analysis methods, and signoff criteria for SoC I/O subsystems—bandwidth, latency, QoS, ordering, flow control, topology, and congestion. 

• Build, extend, and apply performance models to evaluate architectural options early and answer design questions with data-driven recommendations. 

• Analyze performance data from models, simulation, emulation, firmware/software tests, traces, and counters, and correlate pre-silicon predictions against RTL, emulation, and post-silicon results. 

• Create reusable workloads, synthetic traffic patterns, trace-replay methods, benchmark flows, and KPI-correlation techniques that scale across teams. 

• Partner with architecture, design, DV, emulation, firmware, software, validation, and platform teams, communicating tradeoffs clearly in reviews, readouts, and written recommendations. 

• Develop automation and AI-assisted workflows to speed sweeps, data reduction, triage, report generation, and model-based exploration. 

PREFERRED EXPERIENCE 

• Familiarity with high-performance I/O, interconnect, memory, and coherency technologies such as PCIe, CXL, IOMMU/SMMU, UALink, Ethernet, InfiniBand, NVLink, UCIe, AXI, CHI, coherent fabrics, or DMA engines. 

• Hands-on experience building or using performance models—analytical, event-driven, or transaction-level—with C++, Python, or SystemC/TLM. 

• Comfort working with performance data from simulation, emulation, firmware/software tests, traces, counters, benchmarks, and silicon debug tools. 

• Demonstrated technical leadership, cross-team influence, and a track record of using performance evidence to shape product or silicon direction. 

ACADEMIC CREDENTIALS 

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline—or equivalent practical experience. Candidates with different but relevant backgrounds are encouraged to apply. 

LOCATION: 

Vancouver, British Columbia

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