Principal Engineer, Design Verification Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at www.analog.com and on LinkedIn and X.

          

Employer: Analog Devices, Inc.  

Job Title: Principal Engineer, Design Verification Engineering

Job Requisition: 1010.1462.6 / R263318 

Job Location: Austin, Texas

Job Type: Full Time

Rate of Pay: $197,600 - $250,920 per year

Duties:                        

Verification of digital designs and sub-systems using leading edge verification methodologies. Contribute and influence the decisions on methodologies to be adopted for the verification. Architect the testbench and develop the test infrastructure in System Verilog and UVM. Integrate the block level testbench in chip-level UVM environment and verify integration. Define test plans, tests and verification methodology for block / chip level verification. Work with the design team in generating test-plans and closure of code and functional coverage. Continuous interaction with design teams in enabling top-level chip verification. Support post silicon verification activities of the products working with design, product evaluation, and applications engineering team.

Partial telecommute benefit (2 days/week work from home).

Requirements: Must have a Master’s degree in Electrical Engineering, Computer Engineering or closely related technical discipline (willing to accept foreign education equivalent) and ten (10) years of experience as a Design Verification Engineer or related occupation performing pre-silicon design verification.

Must also possess the following (quantitative experience requirements not applicable to this section):

• Demonstrated Expertise (“DE”) developing test benches using System Verilog and OVM or UVM including test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, and assertion-based verification techniques.

• DE in Verilog, C or C++, revision control systems such as Perforce or Git, EDA tools and scripting (Python, Perl or Shell) used to build infrastructure, tools, and flows for verification environments.
• DE architecting and implementing Design Verification infrastructure and executing the full verification cycle. DE with pre- and post-silicon verification test flow and automated test benches.
• DE with verification of ARM or RISC-V based sub-systems or SoCs.

Contact: Eligible for employee referral program. Apply online at https://www.analog.com/en/careers.html and Reference Position Number: R263318.

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

EEO is the Law: Notice of Applicant Rights Under the Law.

Job Req Type: Experienced

          

Required Travel: No

          

Shift Type: 1st Shift/Days