Manage and lead a team of physical design engineers. Job also entails significant amount of handson work, in particular placeandroute, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with frontend engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting.
Desired Skills & Experience:
Must possess 10+ years of hands on experience in handling blockchip level implementation from Netlist to GDS
Must possess hands on experience in timing closure and physical verification closure
Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
Experience in handling lower tech nodes that include 40nm, 28nm or lesser nodes etc.
Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter or mentor tools.
Must have the ability to think on the spot for quick solutions and workaround at the time of tapeout to hit the schedule on time
Must possess excellent scripting skills – TCL or Perl
Experience in Synthesis and Formal is a plus
Excellent verbal and written communication skills are required.
Must possess excellent debug skills, analytical skills and the ability to work independently.
Must be highly motivated and possess excellent team spirit
Primary Skills:
Ability to lead a team size of minimum of 10 members who can handle Subsystem PNR activities , Subsystem timing closure and Subsystem physical verification
Secondary Skills:
Knowledge in Subsystem Synthesis, Subsystem IR drop, Subsystem Lec, Subsystem CLP
