Leadstack Inc. is an award-winning, one of the nation's fastest-growing, certified minority-owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.
Job Title: DV Engineer Duration: 06 Months
Location: San Jose, CA
Pay Range: $65 - $75/hour on W2
Vertical Description:
3+ year experience in Austin; 5+ year experience in SJC(mostly working remotely with design and DV team in Austin, so needs to work independently)
- Developing and Implementing Verification Plans
- Building Testbenches using Universal Verification Methodology(UVM)
- Writing Test cases with both constrained-random and directed test cases to thoroughly exercise the design
- Analyzing Simulation Results to identify and debug functional failures, working closely with design engineers
- Debugging; identifying and resolving functional failures in the design, often in collaboration with design team
- Collaborating with Teams: working with design, Cmodel and GC-level DV to ensure design quality and efficient verification closure
Requirements:
Essential Skills & Qualifications: - SystemVerilog: proficient in SystemVerilog for developing testbenches and test cases, - UVM: solid understanding and practical experience with UVM (Universal Verification Methodology) - Debugging: strong debugging skills to identify and resolve functional failures - Verification Planning: experience in developing and executing verification test plans - Collaboration: Ability to work effectively in a team environment - Communication: strong verbal and written communication skills - Problem-Solving: Ability to independently solve complex problems and proposed solutions
