Logo for Altera

Principal Logic Design Engineer

Roles & Responsibilities

  • 15+ years of experience with a bachelor's or master's degree in electrical engineering, computer engineering, or a related field
  • Experience with SystemVerilog, VCS/Synopsys simulators, lint and synthesis
  • Proficiency in programming languages such as C/C++/Perl/Python/TCL/Unix shell scripting
  • Experience in FPGA design and programming

Requirements:

  • Participate in design development tasks throughout the IP development flow
  • Develop logic design, RTL coding, and simulation for IPs, including generation of cell libraries, functional units, IP blocks, and subsystems for full-chip integration
  • Apply strategies, tools, and methods to write RTL and optimize the logic to meet IP release requirements
  • Involve in IP design example bring-up on hardware, hardware verification, and failure debugging

Job description

Job Details:

Job Description:

Altera, a leader in programmable solutions from cloud to edge, delivers cutting-edge FPGA, CPLD, and IP technologies. We are driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure. Our mission is to empower engineers to design and deploy advanced systems with unmatched flexibility and performance.

We are seeking a talented Logic Design Engineer to develop and optimize mixed-signal and high-speed IPs for integration into full-chip designs.

Key Responsibilities:

1. Participate in design development tasks throughout the IP development flow.

2. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP.

3. Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.

4. Applies various strategies, tools, and methods to write RTL and optimize the logic to quality the design to meet the IP release requirement.

5. Involve in design example creation, simulation example creation, IP integration and release process.

6. Involve in IP design example brings up on hardware, hardware verification and failure debugging.

Qualifications:

1. 15+ years' experience with bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.

2. Experience in System Verilog, VCS/Synopsys simulators, Lint and Synthesis

3. Experience in programming with C/C++/Perl/Python/TCL/Unix Shell script

4. Experience in FPGA design and programming is a plus.

5. Experience in RTL validation is a plus.

6. Ability to work with different teams, good communication and problem-solving skills.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

New Delhi, India (Remote)

Additional Locations:

Bengaluru, Karnataka, India

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Related jobs

Other jobs at Altera

We help you get seen. Not ignored.

We help you get seen faster — by the right people.

🚀

Auto-Apply

We apply for you — automatically and instantly.

Save time, skip forms, and stay on top of every opportunity. Because you can't get seen if you're not in the race.

✨

AI Match Feedback

Know your real match before you apply.

Get a detailed AI assessment of your profile against each job posting. Because getting seen starts with passing the filters.

Upgrade to Premium. Apply smarter and get noticed.

Upgrade to Premium

Join thousands of professionals who got noticed and hired faster.