Design Verification(VLSI domain)apgemini

Work set-up: 
Full Remote
Contract: 
Experience: 
Mid-level (2-5 years)
Work from: 

Offer summary

Qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field., 4+ years of experience in VLSI design verification, especially in IP and SoC verification., Proficiency in Verilog, SystemVerilog, and UVM/OVM methodologies., Experience with scripting languages like Perl, Python, Shell, or Tcl is preferred..

Key responsibilities:

  • Verify IPs and SoCs to ensure first silicon success.
  • Define verification strategies, write test plans, and develop test benches.
  • Implement code and functional coverage, assertions, and utilize industry-standard methodologies.
  • Work on various verification activities including GLS, emulation, and protocol verification.

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Job description

Location:bangaloreHyderabadNoida
Job Description

· You will be part of the team verifying IPs and SoCs leading to first Si success.
· IP verification is coverage driven using latest industry standard methodologies and HVLs.
· Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.
· Code coverage, Functional coverage and assertions are desired.
· ARM based SoC verification experience is an added advantage.
· Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.
· Multiple positions with emphasis on AMS and Power aware verification.
· Should have worked on GLS.
Experience4+ years

Primary Skills

· Verilog, SV, UVMOVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl.

Secondary Skills

· Test bench model VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHBAXIAPB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSIDSI, LPDDR.

Required profile

Experience

Level of experience: Mid-level (2-5 years)
Spoken language(s):
English
Check out the description to know which languages are mandatory.

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