Offer summary

Qualifications:

Minimum 5 years of experience in Synthesis and Static Timing Analysis., Hands-on experience with Logical Synthesis, Equivalence Checking, and STA., Proficiency in DMSA flow and timing closure at subsystem, block, and chip levels., Strong scripting skills in TCL and familiarity with UNIX environment..

Key responsibilities:

Lead and mentor a team of 4-5 members in STA and Synthesis activities.

Coordinate with RTL design, Physical design, and DFT teams.

Manage timing fixes using ECOs and develop constraints.

Ensure timely delivery of STA and synthesis tasks.

Job description

Company:HCL

Location:Bangalore

Please share 5+yrs STA lead profiles, location Bangalore.

Below is the JD for STA Lead 5+yrs.

Please share the resource on priority.

STA Synthesis (Design Implementation) Lead LD:● Handon Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
● Handson experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
● Handson the DMSA flow to fix pre and post STA timing.
● Knowledge on the Timing closure on Sub system level & Block level and Chip level.
● Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
● Knowledge on constraint development.
● Good Knowledge of TCL scripting and UNIX env.
● Leading the team 4 to 5 team members by guiding and mentoring on the STA Synthesis.
● Should Coordinate with design team counterparts in RTL design, Physical design and DFT.
● Good communication skills and client interface role.