ASIC Verification ManagerKochi

Work set-up: 
Full Remote
Contract: 
Full time
Experience: 
Senior (5-10 years)
Work from: 
India

Offer summary

Qualifications:

Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or related field., Proven experience in ASIC and FPGA verification, including test bench development., Strong proficiency in SystemVerilog, UVM, and simulation tools like Synopsys VCS or Cadence IES., Knowledge of verification methodologies, assertion-based verification, and scripting in Python or Perl..

Key responsibilities:

  • Lead and build the ASIC verification team in Kochi.
  • Develop verification plans, test bench architectures, and oversee full-chip and subsystem verification.
  • Mentor verification engineers and ensure verification methodology and sign-off criteria are followed.
  • Manage verification activities for ASIC, custom IC, and FPGA designs.

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Owen Mitten Private Limited Startup https://www.owenmitten.com/
2 - 10 Employees
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Job description

Roles & Responsibilities :

Verification of ASIC, custom IC designs, andor FPGA design

Build and lead the verification team.

Drive the test bench architecture, verification plan and test bench development for full chip and subsystem verification.

Mentor and lead a team of verification engineers to complete unit, subsystem and chip level verification.

Develop and maintain methodology, flows, and signoff criteria for verification.

The Ideal Candidate :

Experience with development of test bench architecture, test plan and test bench development for full chip and subsystem verification

Hands on experience with System Verilog and VMMOVMUVM

Handson experience with simulation tools including Synopsys VCS, Cadence IES to verify fullchip SoCs and FPGA based designs

Requires strong understanding of stateoftheart verification techniques, including assertion and metricdriven verification.

Experience in AXI, DDR4, HBM, PCIe verification is a plus

Verification experience in hardware accelerators and coprocessors is a plus

Familiarity with verification management tools including regression management is required

Familiarity with scripting in Python or Perl

Strong understanding of ASIC andor full custom chip development process is required

Experience with FPGA programming and software is a plus

Coherency and computer architecture experience is desirable

Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.

Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques are a plus

Required profile

Experience

Level of experience: Senior (5-10 years)
Spoken language(s):
English
Check out the description to know which languages are mandatory.

Hard Skills

Development TestingVerification And ValidationVerilogChip DesignScriptingSimulation SoftwarePCI ExpressComputer ArchitectureDDR SDRAMDevice SetupAxure RPFormal MethodsAbstraction Layers
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