Job description

Job Details:

Job Description:

Develops and drives end-to-end platform architecture by owning the architectural specification of the platform or board. Translates requirements, key performance, and key experience indicators into platform architecture encompassing hardware, software, SoCs, and other components designed to support a variety of systems, solutions, and applications.
Drives technical readiness of prototype platform design, creates design specification, develops block diagrams and/or high-level designs, and specifies key components, as needed, to meet platform requirements including platform mechanical and thermal architecture. Invents, conceptualizes, and specifies architectural features for next-generation platforms and makes product technology and platform trade-off decisions ensuring platforms conform to standards, specifications, and landing zones.
Provides experimental and proof-of-concept solutions for proposing design alternatives that meet performance, power, area, and timing constraints.
Reviews, challenges, and influences cross-functional roadmaps and technology targets.
Collaborates with other architects, design engineers, and validation engineers to improve the overall design of platform and overcome constraints.
As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry.
Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values.
Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$270k - $310k USD

Qualifications:

Minimum Qualifications

BS in Electrical Engineering, Computer Science or related field
10+ years of experience in design verification at the IP and subsystem levels.
Demonstrated knowledge of System Verilog, UVM, Use of formal and emulation a plus.
Demonstrated understanding of digital design, protocols and silicon architectures.
Proven experience in leading various aspects of IP/subsystem verification etc

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

Oregon, United States (Remote)

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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