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Coherency Verification Engineer

Role overview

Summary

This role focuses on verifying complex digital designs and maintaining verification environments at TechBiz Global's client. You will work with architecture and design teams to ensure specifications are met and contribute to improving verification methodologies.

Qualifications

  • Experience in verification of digital designs at RTL level.
  • Proficiency in SystemVerilog and UVM.
  • Familiarity with CHI protocol and cache-related functionality.
  • Experience with scripting languages such as Python, Perl, Bash, or TCL.
  • Ability to track, document, and communicate verification progress and technical risks.

Responsibilities

  • Verify complex digital designs at RTL level according to architecture and design specifications.
  • Develop and maintain verification environments using SystemVerilog and UVM.
  • Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.
  • Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.

Hard skills

Other skills

  • Collaboration
  • Communication
  • Problem Solving

About the company

TechBiz Global logo

TechBiz Global

  • Staffing & Recruiting
  • Startup
  • 51–200
TechBiz Global is a leading recruitment and software development company. We provide recruitment, IT outstaffing, outsourcing, software development, and customized consulting services focused on making our clients and partners achieve their recruitment goals successfully. Our service packages are flexible to all sizes of companies and industries. At TechBiz Global, we celebrate diversity and promote an inclusive environment. We work with a diverse set of technologies and frameworks. Our international clients and partners extend across more than 20 countries.

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Job description

At TechBiz Global, we are providing recruitment service to our TOP clients from our portfolio. We are currently seeking a Coherency Verification Engineer to join one of our clients' teams. If you're looking for an exciting opportunity to grow in a innovative environment, this could be the perfect fit for you.

Responsibilities:

  • Verify complex digital designs at RTL level according to architecture and design specifications.

  • Develop and maintain verification environments using SystemVerilog and UVM.

  • Create, execute, and debug test plans for block-level, subsystem-level, and top-level verification.

  • Work on the verification of coherent systems, including cache-related functionality and interconnect behavior.

  • Validate designs involving CHI protocol, cache structures, coherency mechanisms, and system-level interactions.

  • Run and manage simulations, regressions, and debug failures using industry-standard verification tools.

  • Apply both formal and dynamic verification methodologies to identify design issues early.

  • Use scripting languages such as Python, Perl, Bash, or TCL to automate verification flows and regression processes.

  • Collaborate closely with architecture, design, and verification teams to analyze specifications, clarify requirements, and resolve issues.

  • Track, document, and communicate verification progress, bugs, coverage status, and technical risks.

  • Contribute to continuous improvement of verification methodology, tools, and best practices.

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