Lead FPGA Development Engineer Leader (m,f,d)

Job Description Summary

Job Description

Roles and Responsibilities:

• Analysing system requirements and defining functions to be implemented in Hardware.
• Strong Knowledge and experience of Model Based Design (MAT LAB Simulink, HDL coder, Xilinx System Generator)
• FPGA Firmware development.
• Analogue and digital Hardware design.
• Maintain legacy products including updates and improvements to extend product life span.
• Contribution to creating and maintaining manufacturing data packs.
• Writing functional specifications for design.
• Writing test specifications (Routine test, Type test, Test Harness).
• Participating in and contributing to design reviews.
• Ensuring designs are documented to Company standards.

Required Qualifications:

• Degree or Higher in Electrical / Electronic engineering or equivalent experience.
• Demonstrable knowledge and experience of Model Based Design.
• Minimum 10+ years' experience of FPGA design using VHDL or Verilog.
• Strong all-round knowledge and understanding of electronic components & principles.
• Exceptional hardware / FPGA debugging skills.
• Experience with Altera, Microsemi, Xilinx FPGA devices and design tools (Quartus II, Libero SoC).
• Dynamic and proactive with ability to work on own or as part of a multi-disciplinary engineering team to resolve technical issues.
• Experience of designing hardware for real time control applications.
• High-speed digital hardware design and PCB layout skills.

Desired Qualifications:

• Experience of designing hardware for real time control applications
• High-speed digital hardware design and PCB layout skills.
• Good verbal and written communication skills.
• Motivated great teammate, self-starter, results oriented.
• Agile development practices e.g., Scrum
• Scripting experience using Perl, Python
• Experience of version control, e.g., SVN, GIT
• Bug tracking tools, e.g., JIRA
• Power Electronics control system design.
• Knowledge of HVDC.

Additional Information

Relocation Assistance Provided: No