Sr. Compiler Engineer

Role: Senior Compiler Engineer

About Tensordyne

Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different modalities and environments - with the ability to quickly learn and then solve complex problems. Tensordyne is an AI system solution company that builds very high-performance, low-power generative AI inference systems. Our mission, through the creation of custom silicon, hardware and software, is to enable multimodal Generative AI inference acceleration at scale, with safe, sustainable, high-performance systems for our hyperscaler and neocloud data center customers. We are at the leading edge of advancing the latest research and product improvements for generative Al inference solutions that will make Al even more advantageous for compelling new generative AI applications. Tensordyne is a well funded, fast-paced startup company with headquarters in both Sunnyvale, CA, and Munich, Germany. We also have many talented team members working remotely across North America and Europe. We take care of our people and their families with comprehensive benefits, competitive compensation, flexible spending options, and recognition programs, because building category-defining technology starts with a healthy, supported team. Come join us as we shape the future of multimodal generative artificial intelligence!

About the Role

The compiler decides whether our inference silicon runs at 30% utilization or 90% or more. That's the job. Together with our team, you'll build the backend that turns AI workloads into microcode for Tensordyne hardware - Napier today and the silicon that follows. This is a clean-slate compiler effort targeting a genuinely unusual architecture. You'll have the opportunity to work on fundamental parts of the compiler.

The users are changing, too. Increasingly, model mapping and optimization will be done by agents as well as engineers. A compiler designed primarily for humans tends to optimize for escape hatches and manual control. A compiler designed to work effectively with agents needs transparent cost models, structured feedback, machine-readable diagnostics, and fast closed-loop iteration. We need both in the same stack and very few teams are building for this interaction today.

What You'll Do

• Contribute to backend compilation end to end: lowering, instruction scheduling, register and resource allocation, and microcode generation.
• Consider the memory hierarchy: SRAM residency, HBM traffic, DMA orchestration, layout, rematerialization, and data movement. The goal is simple: keep the machine compute-bound rather than waiting on memory.
• Develop tiling, fusion, and software-pipelining strategies that close the gap between theoretical and achieved throughput.
• Design compiler interfaces that work for both agents and engineers: structured IR access, machine-readable diagnostics, searchable tuning spaces, and actionable performance feedback.
• Solve problems conventional batch compilers often avoid: dynamic shapes, compile latency, KV-cache management, and the different optimization objectives of time-to-first-token (TTFT) versus steady-state throughput.
• Build cost models that predict performance on silicon that doesn't exist yet, then continuously calibrate those models against real hardware.
• Feed compiler learnings back into ISA and microarchitecture requirements for the next generation of silicon.

What We're Looking For

• Production compiler experience in code generation, optimization, or graph mapping. Tell us what you shipped and what it achieved, not how many years you've been doing it.
• Experience with MLIR and/or LLVM, with meaningful contributions to an active compiler stack such as LLVM, MLIR, TVM, IREE, XLA, Triton, Inductor, or an equivalent internal system.
• Strong modern C++ skills and a disciplined approach to testing and correctness. Rust experience is a plus.
• Experience targeting custom accelerators or non-standard ISAs. You should be comfortable reading a microarchitecture specification, understanding its implications, and arguing with its assumptions when the compiler says they don't hold.
• Strong performance intuition: memory hierarchy, data movement, parallelism, synchronization, occupancy, and the factors that determine whether theoretical hardware throughput becomes real throughput.
• A co-design mindset. Compiler, kernels, runtime, ISA, and silicon are one system. You'll cross those boundaries whenever that's where the performance opportunity is.

What Stands Out

• Defensible opinions about what today's ML compilers get wrong and evidence behind them.
• Work on autotuning, auto-scheduling, or polyhedral compilation.
• Serious hands-on experience using agents in compiler, kernel-generation, or optimization loops.
• CUDA/Triton expertise, particularly with the CUTLASS or NCCL ecosystems.
• Experience with VLIW, systolic, dataflow, or other unconventional architectures.
• Open-source compiler contributions we can read and discuss.

Tensordyne is an equal opportunity employer. We believe that a diverse team is better at tackling complex problems and coming up with innovative solutions. All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

A note to Recruitment Agencies: Please don’t reach out to Tensordyne employees or leaders about our roles -- we’ve got it covered. We don’t accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes. Thank you for your understanding.