Principal DFT Engineer

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Principal DFT Engineer

Job Description:
Developing silicon for AI Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments.

As a Principal DFT(Design for Test) Engineer, you will lead our testing strategy, ensuring the manufacturing quality, reliability, and test efficiency of complex, high-performance AI accelerators.

Key Responsibilities:
Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST.

Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers.

Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory/Logic BIST.

Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis.

Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time.

Technical Requirements:
Experience: 10+ years in DFT, with at least 2 years in a leadership or principal role.

Tools: Mastery of industry-standard tools (e.g., Synopsys TestMAX, Siemens/Mentor Tessent, or Cadence Genus/Modus).

Memory & Logic Test: Deep expertise in MBIST (Memory Built-In Self-Test) with repair capabilities, SCAN, IJTAG (IEEE 1687) and boundary scan (IEEE 1149.1/6).

Advanced Nodes: Proven track record with FinFET nodes (7nm, 5nm, or below).

Low Power: Experience managing DFT in multi-voltage/power-gated designs—crucial for edge efficiency.

The salary range for this position is $180,000 to $220,000 per year. Actual compensation offered will be determined based by factors as job-related knowledge, skills and experience.