ASIC Design Engineer – DSP for Optical transmission

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.

Join a team shaping the future of coherent optical technology. The Wavelogic family of products is widely used across Ciena’s optical fiber transmission solutions and remains one of the key contributors to Ciena’s success in the telecommunications industry.

At Ciena, digital design engineers play a pivotal role, In this role, you will propose innovative digital design solutions to develop power‑ and area‑optimized functional blocks for the Wavelogic product family. This is an opportunity to collaborate with leading architects, systems engineers, and verification experts to bring complex, high‑speed digital designs to life—driving meaningful impact in one of the most advanced areas of telecommunications.

How you will make an impact:

• Interpret architecture and functional requirements to define and refine digital design specifications
• Develop, integrate, and optimize RTL and C/C++ models to enable high‑performance, power‑efficient hardware blocks
• Partner closely with systems, analog, and verification teams to validate functionality and enhance overall design robustness
• Support simulation, regression debugging, and verification coverage closure
• Contribute technical insights, assertions, and reviews that strengthen design quality and reduce development risk
• Participate in lab validation activities for prototypes and product builds
• Maintain clear tracking of issues and communicate progress to project stakeholders.

The must haves:

• 3+ years of experience in digital design for complex hardware circuits
• MEng/MSc degree in electrical engineering, computer engineering, computer science, or related technical discipline
• Hands‑on expertise with C++ development for High‑Level Synthesis (HLS)
• Proficiency in generating RTL from C++ models using CatapultC or Stratus
• Strong knowledge of SystemVerilog for RTL implementation
• Solid understanding of timing, power, and area trade‑offs in hardware design
• Effective communication and collaboration skills, including basic German language capability.

Nice to haves:

• Experience with digital backend flows using Synopsys or Cadence tools
• Familiarity with low‑power digital design techniques
• Background in developing DSP algorithms for hardware
• Exposure to coherent DSP architectures
• Knowledge of protocols such as Optical Transport Network (OTN), B100G, and Ethernet
• Experience with Jira for issue tracking and GIT for source management
• Programming familiarity with Python, Make, Bash, C, and object‑oriented concepts

At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard.  Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.