FPGA Simulation / Verification Engineer

Unlock the power of Safety- and Mission-Critical Engineering with QDSS. We are seeking exceptional individuals to join our elite team- where your expertise will make an impact that matters. Elevate your career in a company dedicated to excellence and the pursuit of safety and mission success. 

Quest Defense Systems & Solutions (QDSS) is supporting the verification of a complex aerospace data management platform and is looking for FPGA Simulation / Verification Engineers with strong UVM experience.

This role centers on developing and enhancing a SystemVerilog/UVM-based verification environment for safety-critical FPGA designs. You will work alongside a senior verification team to build scalable testbenches, develop sequences, debug RTL issues in simulation, and ensure compliance with DO-254 DAL A standards.

The ideal candidate brings deep hands-on experience in UVM testbench development, strong debugging skills, and a solid understanding of digital design and FPGA verification methodologies.

Due to the nature of the project, all applicants must be U.S. citizens.  

This role is remote with a preference for candidates who live or are willing to relocate to Cedar Rapids, IA.

Required Qualifications:

• Bachelor's Degree in electrical, computer or software engineering from an accredited college of university.
• 10+ years of relevant FPGA Verification experience.
• Ability to Construct FPGA Test Bench using UVM Components.
• Deep experience with System Verilog
• Experience with Sequence Development
• Experience with developing DO-254 related documents including but not limited to: Test Plans, Test Procedures, Test Cases, Maintaining a Trace Matrix
• Troubleshooting RTL Design Flaws using Simulation Environment.
• Ability to take a problem and come up with a solution.
• Familiarity with Unit level testbenches
• Familiarity with Chip Level testbenches

Preferred Qualifications:

• Experience developing UVM Predictors and Scoreboards to Implement Self-Checking Simulation Tests.
• Familiarity with Register Modeling and Predicting Register Behavior.
• Proficiency in developing UVM Agents, Drivers, Monitors, and Sequence Items.
• Experience with Code Coverage Analysis for RTL Source (Statement, Branch, FSM, FSM Transition)

Technologies & Tools:

• SVN
• Mentor Graphics Questasim
• Verilog
• VHDL

The QDSS Advantage:  

At QDSS, our advantage is purpose-driven work, collaborative teams, and complex challenges that push boundaries and build lasting impact. You’ll grow your career while contributing to mission-critical programs that demand excellence and shape the future. 

What You’ll Find Here 

• Work That Matters – Next-generation, safety- and mission-critical projects where your contributions have real-world impact. 
• Growth That’s Supported – Competitive compensation, employer-matched 401(k), certification assistance, and clear opportunities for advancement. 
• A Culture That Works – A flexible, collaborative, and people-first environment where teamwork, innovation, and balance are valued. 

Benefits Include 

• Competitive pay, comprehensive medical/dental/life and disability coverage, 401(k) with employer match, professional development support, and a flexible, friendly workplace.