Principal AMS Verification Engineer (m/f/d)

As Senior / Principal Verification Engineer, you will:

• Work with the global design teams to do complex SOC verification for digital/analog/FW design

• Be responsible for verification plan quality, verification result/design target cross-check, test case development to reach better coverage and verification quality

• Co-work with functional verification team to ensure the complex SoC verification functional coverage and quality

We are looking for:

• 5+ years hands-on experience in Chip-Level AMS Verification on medium-complex designs, for example Transceivers Systems having: variable boot-up sequences; diverse operation-modi; diverse supply domains; diverse communication protocols

• In this context, it is required specific knowledge about: writing an exhaustive Top-Level AMS verification plan; setting-up an AMS flow, harmonizing it to the Digital Verification flow; techniques for minimizing simulation time and maximizing coverage

• Knowledge of the Analog and Digital Design Flows, with hands-on experience on at least one of the two

• Knowledge of the Cadence AMS suite

• Scripting/Language skills (in bold the required ones): C/C++, Bash, Python, Verilog / VerilogAMS, System-Verilog, Tcl, WREAL

• Ability to visually inspect analog circuits and/or digital blocks to grasp their main functionalities

• Knowledge of Cadence Virtuoso/Spectre, vManager, vPlan is an advantage

• Familiarity with revision control software (e.g. DesignSync, SVN) is an advantage

• Additionally we regard of primarily importance the following skills / abilities: ability to drive diverse tasks involving several stakeholders (i.e. Analog Architect, Digital Architect, System Architect, Project Leader, Designers) for accomplishing the system verification; ability to work independently; self-driven mentality

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