Key Facts

Remote From:

Freelance

38 - 38K yearly

English

Hard Skills

Verilog Direct Programming Interface Memory Architecture Engineering Documentation Block Design State Diagram IEEE Standards Association Logic Systems Timing Diagrams Circuit Diagrams Microarchitecture Specification Conformance

Other Skills

•
Detail Oriented

Roles & Responsibilities

Recent graduates or junior-level hardware / digital design engineers
Background in digital systems, hardware design, or related technical fields
Ability to understand and produce technical artefacts and documentation

Requirements:

Create and curate dataset records consisting of one diagram image plus an associated technical artefact (HDL code for Variant 1 or English technical description for Variant 2) in alignment with project guidelines
Maintain the target distribution across diagram categories (circuit diagrams, timing diagrams, and state diagrams) with a balance within ±3% and ensure the 50/50 split between variants
Apply technical requirements: ensure at least 60% gate-level diagrams, keep simple diagrams under 30%, and accept both gate-level and block-level diagrams within those limits; use Verilog/SystemVerilog (IEEE 1364 family) and allow VHDL up to 10% of Variant 1
Produce high-quality artefacts and documentation, ensuring technical realism and alignment with industry standards (e.g., AMBA AXI) for dataset usefulness

Summa Linguae Technologies

About Summa Linguae Technologies

Summa Linguae Technologies is a language and technology service provider headquartered in Poland with 7 offices located across North America, Europe, and Asia.  We specialize in technology-enabled localization, managed services, and data solutions.    Intent on transforming the traditional approach to language, Summa Linguae is one of the industry's fastest-growing companies. We take an outcome-based approach, tailoring solutions to our customers' specific needs. Our promise is to help global, content-rich companies with every multilingual data challenge.    To learn more about Summa Linguae Technologies, our journey, and the solutions we offer, visit: https://summalinguae.com/. 

Company type: SME

Founded: 2018

Company size: 201 - 500

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Job description

DATAmundi.ai is looking to onboard a high volume of junior-level technical resources to support Technical Dataset Creation (Hardware / Digital Systems).

Resource Profile

Recent graduates or junior-level hardware / digital design engineers
Background in digital systems, hardware design, or related technical fields
Ability to understand and produce technical artefacts and documentation

Location

Remote – open to candidates from any country

Engagement Details

Indicative hourly rate: ~USD 20/hour
Expected scale: 50–100 experts
The scope may be reduced at a later stage, but a relatively high onboarding volume is currently expected

Project Overview

The goal of the project is to build a dataset of 200 000 images focused on:

hardware design
digital system diagrams

Each data record consists of:

1 diagram image
1 associated technical artifact

The dataset is split 50/50 across the following two variants:

Variant 1

Diagram image + associated HDL code
Primary languages:
- Verilog
- SystemVerilog
Supported standards:
- IEEE 1364
- IEEE 1364-2001 Rev. C
- IEEE 1800-2009
- IEEE 1800-2023
VHDL is permitted for up to 10% of the Variant 1 volume (optional)

Variant 2

Diagram image + English technical description accurately explaining the diagram

Diagram Categories (3-way split)

A balanced distribution is required across:

Circuit diagrams
Timing diagrams (waveforms)
State diagrams (finite state machines)

Target distribution must remain within ±3% tolerance per category.

Technical Requirements

At least 60% gate-level diagrams
Simple diagrams must not exceed 30% of the dataset
Both gate-level and block-level diagrams are acceptable within these limits
Technical coverage includes:
- memory chips
- processors
- digital and logical circuits
Industry-standard references (e.g. AMBA AXI) may be used to ensure technical realism