Design Verification Engineer (DV)

Job Title: Design Verification Engineer (DV)
Experience Required: 5 to 10 Years
Duration: 12 months
Job Location: (Netherlands / Remote from Europe)

Job Summary:

We are seeking an experienced Design Verification Engineer with a strong background in SoC/IP verification, particularly within the ARM ecosystem. The ideal candidate will possess a high level of expertise in System Verilog, UVM methodology, and functional/code coverage. In addition to technical acumen, solid communication and analytical skills are essential for customer interfacing and team collaboration.

Key Responsibilities:

• Perform SoC and IP-level verification using System Verilog and UVM.
• Work on verification of ARM-based SoCs.
• Integrate and use PCIe VIP for verification; hands-on experience with PCIe protocol is essential.
• Execute GLS (Gate Level Simulations) and analyze results.
• Develop and analyze functional and code coverage metrics.
• Collaborate with design, architecture, and software teams for verification planning and execution.
• Manage version control and collaboration using GIT.
• Coordinate effectively with both onsite and offshore teams.
• Interface with customers as needed and support project milestones.

Qualifications:

• Bachelor’s or master’s degree in electrical/Electronics/Computer Engineering or related field.
• 5 to 10 years of experience in ASIC/SoC verification.

Nice to Have:

• Experience in formal verification or low-power verification flows.
• Exposure to scripting (Python/Perl) for automation.

Recruitment Firm:

This recruitment is being managed by Sperton Global.