FPGA Verification_Mayumi
Offer summary
Qualifications:
4 to 12 years of experience in FPGA Verification using VHDL and SystemVerilog., Proficiency in UVM/OVM methodologies., Experience with testbench development, waveform analysis, and verification components., Knowledge of scripting languages such as Python, Perl, or TCL..Key responsibilities:
- Develop and verify FPGA designs using VHDL and SystemVerilog.
- Create and maintain testbenches, testcases, and verification components.
- Analyze waveforms and debug verification issues.
- Utilize version control tools like GIT, SVN, or ClearCase.
Job description
• 4 to 12 Years of experience in FPGA Verification using VHDL, System Verilog, UVMOVM.
• Experience in Testbench, Testcases, Waveform Analysis, Minotors, Checkers & Scoreboard.
• Scripting language for automation Python Perl TCL
• GITSVNClear Case tools
Required profile
Experience
Level of experience: Senior (5-10 years)
Spoken language(s):
English
Check out the description to know which languages are mandatory.