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Design Verification Engineer_Tanvi_Coders Brain

CodersBrain

Key Facts

Remote From: 
India
Full time
Mid-level (2-5 years)
English

Roles & Responsibilities

  • Minimum of 3 years experience in SystemVerilog and UVM.
  • Expertise in Ethernet, DDR, or PCI-Express protocols.
  • Proficiency in scripting languages.
  • Relevant educational background in electronics or related fields.

Requirements:

  • Perform design verification using SystemVerilog and UVM.
  • Develop and execute test plans for hardware components.
  • Collaborate with design teams to identify and resolve issues.
  • Document verification results and contribute to project reports.

Job description

JD for Design Verification:
  • 3+ years of System Verilog + UVM experience
  • Ethernet, DDR or PCIExpress expertise
  • Scripting experience
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