Minimum of 3 years experience in SystemVerilog and UVM., Expertise in Ethernet, DDR, or PCI-Express protocols., Proficiency in scripting languages., Relevant educational background in electronics or related fields..
Key responsibilities:
Perform design verification using SystemVerilog and UVM.
Develop and execute test plans for hardware components.
Collaborate with design teams to identify and resolve issues.
Document verification results and contribute to project reports.
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