Design Verification Engineer_Tanvi_Coders Brain

Work set-up: 
Full Remote
Contract: 
Experience: 
Mid-level (2-5 years)
Work from: 

Offer summary

Qualifications:

Minimum of 3 years experience in SystemVerilog and UVM., Expertise in Ethernet, DDR, or PCI-Express protocols., Proficiency in scripting languages., Relevant educational background in electronics or related fields..

Key responsibilities:

  • Perform design verification using SystemVerilog and UVM.
  • Develop and execute test plans for hardware components.
  • Collaborate with design teams to identify and resolve issues.
  • Document verification results and contribute to project reports.

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CodersBrain SME https://www.codersbrain.com/
201 - 500 Employees
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Job description

JD for Design Verification:
  • 3+ years of System Verilog + UVM experience
  • Ethernet, DDR or PCIExpress expertise
  • Scripting experience

Required profile

Experience

Level of experience: Mid-level (2-5 years)
Spoken language(s):
English
Check out the description to know which languages are mandatory.

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