Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
Experience with DFT techniques, Memory BIST, and Scan testing on complex SoCs.
Proficiency with ATPG and MBIST tools, and knowledge of SOC design flow.
Strong problem-solving, communication, and teamwork skills.
Requirements:
Design and implement DFT techniques for SOCs.
Verify test modes and insert scan chains, including on-chip compression.
Implement and verify memory BIST and boundary scan solutions.
Generate ATPG test vectors and perform gate-level simulations with timing analysis.
Job description
Description:
• Will be responsible for Designing and Implementing DFT techniques
• Should hava a good understanding of Memory BISTScan OnChip CompressionAtspeed ScanTestclockingBoundary ScanAnalog TestingPinmuxingLogicBIST on complex SOCs to improve testability.
• Test Modes implementation and verification, scan insertion including onchip compression.
• Implementing, integrating and verifying memory BIST and boundary scan .
• ATPG Test vector (StuckatAtspeedPath delaySDDIDDQBridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
• Basic understanding of complete SOC design and flow.
• Excellent in problem solving and analytical skills
• Excellent communication, team work and networking skills
Primary Skills
• Should Have Good understanding of Design and DFT Architecture
• Should have been part of Tapeout SoC
• Well Versed with ATPG Tools & MBIST Tools
•
Secondary Skills
• Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders)
• Familiarity with Desired Flexibility and adaptability with respect to project management
