Principal DFT Engineer

Work set-up: 
Full Remote
Contract: 
Full time
Experience: 
Senior (5-10 years)
Work from: 
Greece, Estonia, Latvia, Republic of Lithuania, Finland, Ukraine, Hungary, Bulgaria, Poland, Romania, Portugal, Spain, Denmark, United Kingdom, Switzerland...

Offer summary

Qualifications:

Senior-level expertise in DFT engineering., Proficiency in SystemVerilog RTL, TCL, Python, and Unix/Linux., Knowledge of hierarchical scan, ATPG, Memory BIST, JTAG/IJTAG, fault simulation, silicon debug, and gate-level verification., Familiarity with Siemens, Cadence, or Synopsys DFT tools..

Key responsibilities:

  • Develop and implement DFT strategies for multicore in-memory-compute SoCs.
  • Collaborate with cross-functional teams to ensure seamless integration of test solutions.
  • Drive innovation by advancing testability methodologies and infrastructure.

Axelera AI logo
Axelera AI Scaleup https://axelera.ai/
51 - 200 Employees
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Job description

About Us

Axelera AI is not your regular deeptech startup. We are creating the nextgeneration AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just three years, we have raised a total of $120 million and have built a worldclass team of 180+ employees (including 55+ PhDs with more than 40,000 citations), both remotely from 11 different countries and with offices in Belgium, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis™ AI Platform, which achieves a 35x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Are you up for the challenge?

Position Overview

Join a leading European semiconductor startup, as a Design for Test (DFT) Engineer. Play a pivotal role in architecting and implementing innovative testability solutions for our multicore inmemorycompute SoC. This is an opportunity to contribute to cuttingedge semiconductor advancements in a collaborative and dynamic environment.

Key responsibilities:

Required profile

Experience

Level of experience: Senior (5-10 years)
Spoken language(s):
English
Check out the description to know which languages are mandatory.

Hard Skills

Tcl (Programming Language)Direct Programming InterfacePython (Programming Language)UnixStatic Timing AnalysisIEEE Standards AssociationDesign Flow

Other Skills

  • Communication
  • Problem Solving
Are you interested?

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