Experience in microarchitecture, synthesis, and timing closure.
Knowledge of ASIC design tools like VCS, Verdi, and Design Compiler.
Background in power estimation, optimization, and hardware architecture exploration.
Requirements:
Design and optimize RTL for low power and area efficiency.
Use ASIC tools for synthesis, verification, and power estimation.
Collaborate on microarchitecture development and performance modeling.
Apply knowledge in machine learning or memory controllers is a plus.
Job description
1. Experience in Low power RTL design, microarchitecture, synthesis, timing closure, power estimation. Should be proficient in Verilog.
2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.
3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.
4. Experience with hardware architecture exploration, performance modelling will be a big plus. 5. Prior experience in Machine learningArtificial Intelligence domain andor DRAM Memory controllers is a plus.
