Key Facts

Remote From:

Fixed term

Senior (5-10 years)

English

Hard Skills

Identity And Access Management Cadence Virtuoso Data Partitioning Electronic Design Energy Management Unix Space Planning Tcl (Programming Language) Perl (Programming Language)

Roles & Responsibilities

Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field.
Extensive experience (4-15 years) in SOC physical design and PNR activities.
Proficiency in EDA tools such as Synopsys ICC, Cadence, or Mentor Olympus.
Strong understanding of timing closure, power planning, and physical verification techniques.

Requirements:

Perform SOC floorplanning, partitioning, and power planning.
Handle timing closure and physical verification at both block and chip levels.
Manage SOC PNR activities, including signoff closure and constraint fixing.
Coordinate with teams to ensure design signoff and physical implementation quality.

Job description

Location : Bangalore

SOC Physical design : 4 – 15 years
Location: Bangalore

Skills:Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration
Handling timing closure of high frequency blocks.
Expertise in signoff closure – Timing with SI and OCV, Power, IR and physical verification at both block and chip level.
Understanding constraints and fixing techniques.
Experience in physical verification
Understanding SI prevention, fixing methodology and implementation.
Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set.
Experience in Design Automation and UNIX system.
Experience in Tcl PERL is a plus.

Primary Skills:Able to handle Soc PNR activities , SOC timing closure and SOC physical verification

Secondary Skills:Able to handle SOC Synthesis, SOC IR drop, SOC Lec, SOC CLP