Key Facts

Remote From:

India

Full time

Senior (5-10 years)

English

Hard Skills

Static Timing Analysis Formal Equivalence Checking Chemical Synthesis Constraint Management Unix

Other Skills

•
Mentorship
•
Team Leadership
•
Communication

Roles & Responsibilities

Minimum 5 years of experience in STA and synthesis.
Hands-on expertise in static timing analysis and synthesis tools.
Knowledge of TCL scripting and UNIX environment.
Strong leadership and communication skills to lead a team and coordinate with design teams.

Requirements:

Lead and mentor a team of 4-5 members in STA and synthesis activities.
Coordinate with RTL design, physical design, and DFT teams.
Manage timing closure at subsystem, block, and chip levels.
Oversee manual ECOs and constraint development to fix timing violations.

Job description

Role: STA lead

Location: Bangalore.

Experience: 5+ Y

Company Name: HCL

Notice Period : Immediate to 30 Days

Below is the JD for STA Lead 5+yrs.

STA Synthesis (Design Implementation) Lead LD:● Handon Experience and Comprehensive knowledge of Synthesis and Static Timing Analysis.
● Handson experience on Logical aware Synthesis, Logical Equivalence check and Static Timing analysis.
● Handson the DMSA flow to fix pre and post STA timing.
● Knowledge on the Timing closure on Sub system level & Block level and Chip level.
● Knowledge on Writing Manual ECO’s to fix timing violations and DRC’s.
● Knowledge on constraint development.
● Good Knowledge of TCL scripting and UNIX env.
● Leading the team 4 to 5 team members by guiding and mentoring on the STA Synthesis.
● Should Coordinate with design team counterparts in RTL design, Physical design and DFT.
● Good communication skills and client interface role