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SynthesisSTA_Rakesh_Capgemini

CodersBrain

Key Facts

Remote From: 
India
Fixed term
Senior (5-10 years)
English

Other Skills

  • •
    Problem Solving

Roles & Responsibilities

  • Experience in synthesis of complex SoCs and writing timing constraints.
  • Proficiency in formal verification from RTL to netlist with DFT constraints.
  • Experience in post-layout STA closure and timing ECOs.
  • Knowledge of technology nodes 45 nm and below.

Requirements:

  • Handle SoC/Subsystem and block-level synthesis activities.
  • Perform SoC/Subsystem and block-level LEC, CLP, and timing closure.
  • Debug CTS issues and balance clocks using PTPX.

Job description

STA (Static timing analysis) Engineers: 4 – 15 years
Location:bangalore
Skills:
Experience in Synthesis of complex SoCs block top level and writing timing constraints.
Experience in formal verification RTL to netlist – to netlist with DFT constraints.
Experience in postlayout STA closure and timing ECOs.
Worked in technology nodes 45 nm and below.
Knowledge of low power aware implementation is a plus.
Tools: Design compiler, RTL compiler, LEC, CLP, ETS PTSI GT.
Primary Skills:
Able to handle SocSubsystem and blocklevel synthesis activities , SocSubsystem and blocklevel LEC, CLP and timing closure
Secondary Skills:
Able to handle PTPX and debug CTS issues to balance clocks
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