Midcore CPU Performance Architect

Tenstorrent is looking for a CPU Architect to take the lead on the design and optimization of the Midcore Unit (MC) in our highperformance, outoforder RISCV CPUs. This is a handson architecture role with real impact—you’ll be shaping the performancecritical instruction scheduling and execution units in the CPU. Youll work alongside some of the industrys best minds in highperformance computing and CPU microarchitecture.

This role is remote, based out of The United States.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You have a strong grasp of CPU microarchitecture fundamentals, especially around instruction scheduling, register files, scalar and vector execution, and optimizing instruction execution latencies.
• You have worked with performance simulation tools like Gem5 or SimpleScalar and are comfortable analyzing system bottlenecks and tuning performance.
• You’re collaborative, organized, and enjoy bridging architectural ideas with handson modeling and analysis.
• Familiarity with HDLs (Verilog, VHDL) and lowlevel CC++ programming is a plus—not required, but helpful in collaborating with design and software teams

• What We Need

  • Drive the architecture and microarchitecture of the midcore unit for our outoforder RISCV CPUs.
  • Model, simulate, and evaluate midcore performance and PPA (power, performance, area) tradeoffs, including novel crossunit instruction scheduling and execution techniques.
  • Propose and prototype new approaches to optimize scheduling and execution paths and improve instructiondata throughput.
  • Collaborate with software, RTL, and performance modeling teams to close the loop on realworld performance.

  • What You Will Learn

    • How to architect highthroughput, lowlatency general purpose, AI, and HPC workloads that scale across chiplets and cores.
    • How to model and optimize CPU behavior across different instructionmix patterns and workloads.
    • How Tenstorrent blends RISCV extensibility with custom microarchitecture to push boundaries in highperformance CPU design.
    • How cuttingedge CPU teams deliver innovative performance features from architecture spec to implementation and validation.

    • Compensation for all engineers at Tenstorrent ranges from $100k $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

      Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

      This offer of employment is contingent upon the applicant being eligible to access U.S. exportcontrolled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct andor indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenshippermanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.