Principal Engineer, VLSI Design Engineering

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

We are looking for an experienced Digital Physical Design Engineer to work whole digital SPR flow from RTL to GDS, include Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced Cadence and Synopsys digital flow: Fusion compiler, DCG, ICC2, Innovus, PT, StarRC …

Key Responsibilities

• Synthesis and DFT scan insertion
  • Familiar timing constraint and qualify, clean up timing constraints file in Synthesis.
  • Be able to timing and DFT analysis to improve Synthesis and DFT coverage performance.

• Place and Routing
  • Placement stage timing and routing analysis and improvement.
  • CTS: Clock tree analysis, adjust clock skew, insertion delay to improve clock tree quality and timing.
  • Routing: be able to debug and analysis timing, routing issue in routeOpt stage,

• STA timing analysis
  • MMMC timing analysis using PT and fix timing in PNR.
  • Timing ECO flow using PrimeClosure.

• DRC/LVS/Antenna verification
  • Verify DRC/LVS/Antenna in PNR and Layout and fix violations.

• Team work and Communication:
  • Good team work with team member and others function team.
  • Good communications skill.

Required Skills & Qualifications

• Experience: A minimum of 10 years in Physical design digital RTL to GDS flow.
• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• Programming & Scripting: Proficiency in TCL/TK, Perl scripting.
• EDA Tools: Familiarity with Cadence, Synopsys digital flow include Synthesis, PNR, STA.  Calibre physical verification, Redhawk power analysis.

All your information will be kept confidential according to EEO guidelines.