Summary
We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.
Responsibilities
Required Skills
Dev.Pro
SynergisticIT
SynergisticIT
SynergisticIT
SynergisticIT