Design Verification(VLSI domain)apgemini

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Offer summary

Qualifications:

Bachelor's or Master's degree in Electrical Engineering or related field., 4+ years of experience in VLSI design verification., Proficiency in Verilog, SystemVerilog, UVM/OVM, and scripting languages like Perl, Python, or Shell., Experience with ARM based SoC verification and coverage-driven methodologies..

Key responsibilities:

  • Verify IPs and SoCs to ensure successful silicon outcomes.
  • Define verification strategies and write comprehensive test plans.
  • Develop efficient test benches and test cases for verification.
  • Utilize code coverage, functional coverage, and assertions in the verification process.

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Job description

Location:bangalore/Hyderabad/Noida

Job Description

·      You will be part of the team verifying IPs and SoCs leading to first Si success.
·      IP verification is coverage driven using latest industry standard methodologies and HVLs.
·      Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.
·      Code coverage, Functional coverage and assertions are desired.
·      ARM based SoC verification experience is an added advantage.
·      Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.
·      Multiple positions with emphasis on AMS and Power aware verification.
·      Should have worked on GLS.
      Experience-4+ years

Primary Skills

·      Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting – Perl, Python, Shell, and Tcl.

Secondary Skills

·      Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.

Required profile

Experience

Spoken language(s):
English
Check out the description to know which languages are mandatory.

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