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ASIC Verification Manager-Kochi

Remote: 
Full Remote
Contract: 
Full time
Work from: 
India

Offer summary

Qualifications:

Experience in ASIC and FPGA design verification., Proficiency in System Verilog and verification methodologies like VMM/OVM/UVM., Familiarity with simulation tools such as Synopsys VCS and Cadence IES., Strong understanding of verification techniques and scripting in Python or Perl..

Key responsabilities:

  • Lead and mentor a team of verification engineers.
  • Drive the development of test bench architecture and verification plans.
  • Oversee unit, subsystem, and chip level verification processes.
  • Develop and maintain verification methodologies and sign-off criteria.

Owen Mitten Private Limited logo
Owen Mitten Private Limited Startup https://www.owenmitten.com/
2 - 10 Employees
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Job description

Roles & Responsibilities :

- Verification of ASIC, custom IC designs, and/or FPGA design

- Build and lead the verification team.

- Drive the test bench architecture, verification plan and test bench development for full chip and subsystem verification.

- Mentor and lead a team of verification engineers to complete unit, subsystem and chip level verification.

- Develop and maintain methodology, flows, and sign-off criteria for verification.

The Ideal Candidate :

- Experience with development of test bench architecture, test plan and test bench development for full chip and subsystem verification

- Hands on experience with System Verilog and VMM/OVM/UVM

- Hands-on experience with simulation tools including Synopsys VCS, Cadence IES to verify full-chip SoCs and FPGA based designs

- Requires strong understanding of state-of-the-art verification techniques, including assertion and metric-driven verification.

- Experience in AXI, DDR4, HBM, PCIe verification is a plus

- Verification experience in hardware accelerators and coprocessors is a plus

- Familiarity with verification management tools including regression management is required

- Familiarity with scripting in Python or Perl

- Strong understanding of ASIC and/or full custom chip development process is required

- Experience with FPGA programming and software is a plus

- Coherency and computer architecture experience is desirable

- Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.

- Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques are a plus

Required profile

Experience

Spoken language(s):
English
Check out the description to know which languages are mandatory.

Hard Skills

Development TestingVerification And ValidationVerilogScriptingSimulation SoftwarePCI ExpressDDR SDRAMDevice SetupAxure RPHardware AccelerationFormal MethodsMicroprocessorAbstraction Layers

Other Skills

  • Mentorship
  • Leadership
Are you interested?

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