Offer summary
Qualifications:
BS or MS in Electrical Engineering or related field, 5 years overall experience, 2 years in Hardware Design/Verification, Expertise in HDLs: Verilog, SystemVerilog, VHDL, SystemC, Experience in UVM environments and Formal Verification.Key responsabilities:
- Develop hardware design platform for LLM training data
- Liaise with research teams to refine data insights