Offer summary
Qualifications:
BS or MS degree in Electrical Engineering or related field, 3-5 years of experience in hardware design development, Expertise in HDL languages: Verilog, SystemVerilog, VHDL, SystemC, Experience in UVM environments, Formal Verification, and Lint processes, Good communication skills in English.
Key responsabilities:
- Develop, configure, and customize hardware design platform
- Generate training data for enterprise LLMs
- Liaise with research teams for actionable data insights
- Maintain standards in coding, debugging, and documentation
- Collaborate across teams to prioritize needs for LLM optimization