Senior FPGA/RTL Architect/Engineer (GB)

Signaloid provides a computing platform that tracks data uncertainties dynamically and throughout computations in execution workloads. Our computing platform uses deterministic computations on in-processor representations of probability distributions, to enable orders of magnitude speedup and lower implementation cost for computing tasks traditionally solved using Monte Carlo methods. The platform is available as a cloud-based computing engine that lets you run tasks via a cloud-based task execution API. We also provide on-premises and edge-hardware implementations of our computing platform for customers who want to use their existing on-site infrastructure and for use cases requiring operation without connection to the cloud.

Our platform is the most cost-effective way to engineer uncertainty quantification applications and is also the fastest way to run uncertainty quantification tasks, for key use cases. Workloads ranging from options pricing and portfolio modeling in finance, to uncertainty quantification for materials modeling and photonics simulation in engineering, often run an order of magnitude or more faster, compared to Monte-Carlo-based implementations running on high-end AWS EC2 instances.

Our team consists of contrarian engineers with combined research, engineering, and leadership experience from Apple, ARM, Bell Labs, CMU, University of Cambridge, IBM Research, MIT, NEC Labs, and University of Oxford. Find out more   and try out the Signaloid uncertainty-tracking computing platform by signing up for free for our developer platform, at https://get.signaloid.io.

Role Description

Within the first year in this role, you will:

• Be responsible for the RTL hardware design, FPGA prototyping, cloud-based FPGA deployment, and custom silicon implementation of new microarchitectural components of Signaloid's compute engine.
• Lead the implementation of improvements in performance, reliability, and implementation quality of existing and new microarchitecture components in both C/C++ and Verilog RTL.
• Be responsible for the tools for functional verification of the microarchitecture of Signaloid's processor platforms.
• Be responsible for documenting and communicating architectural design decisions to the wider team.

After a year in this role, you will have the opportunity to:

• Lead new architectural design work across Signaloid's compute architectures.
• Lead the implementation of your own architectural ideas in collaboration with a larger team.
• Contribute to the strategic direction of Signaloid's computing platforms.
• Expand your role to encompass other areas in which you have demonstrated exceptional competence.

Requirements

• Thorough understanding of architectural and microarchitectural concepts and abstractions of modern computing systems.
• Thorough understanding of the required steps from source code compilation to binary execution in modern computing systems.
• Thorough understanding of the practical challenges of implementing digital arithmetic structures in both FPGAs and custom silicon.
• Prior commercial experience with all stages of chip design flow, from RTL to GDS and eventual bringup and an ability to carry out tasks within the flow, from design to bringup, yourself.
• Seven or more years experience with Verilog RTL.
• Seven or more years experience writing low-level C/C++.
• An ability to communicate complex engineering ideas succinctly and clearly.
• Honesty, empathy, and a willingness to see the world from the viewpoint of others.
  

Additional Desirable Attributes, Skills, and Experience:

• Familiarity with Python and Go.
• Familiarity with verification frameworks such as Cocotb.
• Familiarity with cross-compilation toolchains, LLVM, and RISC-V architecture.
• Applied mathematics background (with good working knowledge of probability theory, statistics, Bayesian methods).
• Background in the role of uncertainty in measurements and in engineered systems.

Our Recruiting Procedure

• All positions require you to write a brief cover letter that should be no more than one page long. The more concise the better. You can also substitute the cover letter for a snippet of code that will run on the signaloid.io platform; be creative! We use the cover letter / code snippet to screen for communication skills, as clear communication is essential in a remote working environment.
• Applicants who pass the cover letter screening receive an initial 15-minute Zoom screening call with the CEO/CTO.
• Applicants who pass the screening interview will be given a coding project that can be solved using the Free Tier of Signaloid's Signaloid Cloud Developer Platform. We will also provide you with additional free credits on the Signaloid Cloud Developer Platform. The coding exercise will be simple enough to complete in a few hours. You will however have a time window of one week or two weeks (your choice) to complete the coding exercise. You are encouraged to make your implementation open source on GitHub.
• Applicants who successfully complete the coding exercise are invited for a set of interviews with people from our core teams (there will be up to six interviewers). The interviewers will use the project you completed as a discussion point.
• In the final stage, applicants are invited for an on-site (or "virtual on-site") day with members of the team you are interviewing to join. During this day, we will work with you on a hands-on simulation of a real working day solving a task relevant to the position you are applying for, working with your potential future colleagues.

Benefits

A flexible remote-first work environment

• Be part of an international team with the flexibility to choose where you live, as long as you are available during the working hours of 09:00 to 17:00 UK time.
• Join the rest of the team several times each year for an in-person session somewhere in Europe.

Competitive compensation

• Yearly bonus based on company's Objectives and Key Results (OKR) performance and bi-yearly bonus based on your project team's OKR performance.
• Simple transparent compensation across the company, with four pay levels, in all roles, based on skill level: Contributor, Senior Contributor, Lead Contributor, and Principal Contributor.
• All full-time employees receive attractive stock options package.

A driven but respectful environment

• We never speak ill of others even if we differ in our viewpoints; we show up every day with a sense of urgency; we treat each other with respect as though each day were our last.
• No isolated "projects": No person in the team works in isolation and a successful outcome for the thread of work you lead will inherently depend on getting help from (and helping) other members of the team.