Offer summary

Qualifications:

University degree, ideally a master’s degree, in a relevant field., 2+ years of experience in software and/or RTL related to machine learning acceleration on FPGAs., Experience in both RTL and software is preferred., Familiarity with EMIF/DDR interface performance optimization and SoC development is a plus..

Key responsabilities:

Architect and implement soft IP for advanced machine learning algorithms on FPGAs.

Improve the performance of IP to leverage FPGA flexibility in numerical precision and memory hierarchy.

Add support for new types of machine learning graphs as market needs evolve.

Evaluate forward-looking silicon architectures and optimize IP for new features.

Job description

Job Details:

Job Description:

About the Job

Join Altera, a pioneer in programmable logic solutions, where innovation meets practicality. We empower system, semiconductor, and technology companies to rapidly and cost-effectively differentiate and excel in their markets. Our legacy of innovation is matched by our commitment to our clients, whom we serve through a robust distribution network and a dedicated sales force. Our portfolio spans programmable logic products, acceleration platforms, software, and IP, all designed to accelerate the pace of innovation.

What You Will Do

As a FPGA Machine Learning Overlay and Compiler Engineer you will architect and implement soft IP to implement advanced machine learning algorithms on our FPGAs! Our team creates IP and software that enable customers to integrate advanced ML algorithms into their designs targeting Altera FPGAs. We are responsible for improving the performance of the IP that we provide, to take advantage of the FPGA flexibility in terms of its numerical precision, memory hierarchy, and advanced tensor DSP blocks. You may also become involved in evaluations of forward-looking silicon architectures and optimizing the IP to take advantage of these new undisclosed features. The machine learning space is constantly evolving, and responsibilities of the successful candidate will include adding support for new types of machine learning graphs in the IP, as the market needs adapt in response to the fast-moving machine learning technology.

The successful candidate will join a team with a strong, supporting culture. Our team in turn is part of a larger Altera site that is one of the largest engineering sites within Altera, and recognized for a fun, flexible, and high-performing culture.

Qualifications:

What We Want to See

We are seeking someone with a university degree (ideally master’s degree) and 2+ years of experience, or equivalent academic work, writing software and/or RTL related to machine learning acceleration on FPGAs.

Ways to Stand Out from the Crowd (preferred qualifications)

Experience in both RTL and software

Experience with EMIF/DDR interface performance optimization and SoC development

Job Type:

Regular

Shift:

Shift 1 (Canada)

Primary Location:

Bloor St 1

Additional Locations:

Virtual - CAN

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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