Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.
Creates prototypes, simulates models, and specifies systems requirements.
Prepares and designs logic diagrams and codes for implementing system design and test specifications.
Delivers software models for device level bring up, including user visible functionality, timing, and power.
Applies RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with physical implementation team.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Bachelor’s degree in electrical/Electronic Engineering or Computer Engineering is required .
Experience and knowledge in RTL compilation debug.
Capable of reviewing the design within a broader team.
Basic knowledge of FPGA architecture.
TWL Global Services
Arrow Electronics
SAIC
Overture Rede
Altera