Ciena is committed to our people-first philosophy. Our teams enjoy a culture focused on prioritizing a personalized and flexible work environment that empowers an individual’s passions, growth, wellbeing and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact.
Why Ciena:
We are big proponents of life-work integration and provide the flexibility and tools to make it a reality with remote work and potentially, part-time work.
We believe an inclusive, diverse and barrier-free work environment makes for empowered and committed employees.
We recognize the importance of well-being and offer programs and benefits to support and sustain the mental and physical health of our employees and their families and also offer a variety of paid family leave programs.
We are committed to employee development, offering tuition reimbursement and a variety of in-house learning and mentorship opportunities.
We know that financial security is important. We offer competitive salaries and incentive programs, RSU’s (job level specific) and an employee share option purchase program.
We realize time away to recharge is non-negotiable. We offer flexible paid time off!
Great work deserves recognition. We have a robust recognition program, with ongoing and enhanced awards for exemplary performance.
How You Will Contribute:
Reporting to Director, ASIC Engineering, as a Senior DSP Engineer, you will be a member of the Signal Processing Team involved in the planning, design, integration and testing of next generation high speed optical systems.
You will define and document digital components of Ciena's leading edge optical modems based on functional specifications.
You will plan and schedule design tasks, specify required resources, tools and processes.
You will write object-oriented code in Matlab/C++/CatapultC according to generally accepted coding standards
You will chair code review and document review meetings and publish minutes/features/bugs in Confluence/Jira.
You will supervise, mentor and train junior engineers, and provide ongoing technical feedback.
You will interface and collaborate with hardware-, firmware-, electro/optics, systems- and lab teams.
You will utilize standard lab equipment during ASIC integration and drive/verify the implementation of the new firmware feature.
What Does Ciena Expect of You?
Initiative – you’re a self-starter who works with limited direction and is committed to delivering against aggressive deadlines.
Agility – you are readily able to make key decisions and manage competing and ever-changing account priorities.
Communication expertise – you possess the ability to influence and tailor your message and ideas to ensure understanding and agreement.
The flexibility to work independently and as part of a broader team – you thrive in a multi-disciplinary team environment, but are comfortable working independently as required.
Relationship builder – with an innate ability to influence, you’re able to get work done through others.
Problem solver – with the ability to gather and understand complex system requirements and translate them into discrete signal processing features.
The Must Haves:
Post-graduate degree in Physics or Engineering with a focus on digital hardware, communication and/or control systems coupled with proven experience in the design, implementation, and verification of digital signal processing algorithms for ASIC or FPGA applications.
Authoritative knowledge in digital communication (optical and/or wireless) and signal processing.
Knowledge of all modem design aspects: architecture, simulation, prototyping, verification, integration, control, and optimization.
Experience with automated RTL code generation from high-level system design languages such as CatapultC (HLS).
Programming experience with Matlab, C and C++ (on Linux). Must be willing to learn CatapultC and/or similar hardware design languages.
Experience in ESD-protected lab environment - familiar with standard lab equipment such as oscilloscopes, signal generators, network analyzers, power supplies, and spectrum analyzers.
Assets:
CatapultC, Verilog, Git version control, digital silicon design backend process.
Compensation and Benefits
The annual pay range for this position is $100,900 - $161,100 CAD.
Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.
Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.
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