Offer summary
Qualifications:
10+ years of hands-on ASIC engineering experience, Deep knowledge of VLSI/SoC chip physical design workflows, Experience with EDA tools like Cadence/Synopsys, Bachelor’s or Master's in relevant technical field.
Key responsabilities:
- Lead ASIC front-end physical design and workflow development
- Guide and support colleagues to improve design workflows
- Drive optimization and exploration of frontend physical design technologies
- Collaborate closely with the ASIC team for design and verification