Offer summary
Qualifications:
Bachelor’s or Master’s in Electrical Engineering or related field., Minimum of 5 years in backend ASIC design., Proficient in EDA tools and static timing analysis., Knowledgeable in low-power design and hardware description languages., Experience with UNIX/Linux and version control systems..
Key responsabilities:
- Lead synthesis, optimization, and ensure timing sign-off.
- Develop timing constraints and perform place and route.
- Collaborate with teams for continuous improvement.