Offer summary
Qualifications:
BS or MS in Electrical Engineering, 3-5 years experience in hardware design development, Expertise in Verilog, SystemVerilog, VHDL, SystemC, Experience with scripting and verification workflows, Knowledge of UVM environments and Formal Verification.
Key responsabilities:
- Develop handour design platform for LLMs
- Collaborate with research teams for insights
- Maintain coding, debugging, documentation standards
- Identify and prioritize cross-team needs
- Optimize hardware design solutions for performance