Offer summary
Qualifications:
B.S or MS in Electrical Engineering or equivalent experience, More than 15 years of experience in ASIC development, 7+ years of uArch/Arch definitions in networking ASICs, 6+ years of hands-on experience in Verilog/VHDL.Key responsabilities:
- Define architecture of next-gen switch product lines
- Leverage expertise on Full-Chip correctness and performance
- Collaborate with cross-functional teams
- Thoroughly understand Ethernet, InfiniBand and NvLink protocols