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ASIC Verifier

Remote: 
Full Remote
Contract: 
Experience: 
Mid-level (2-5 years)
Work from: 

Offer summary

Qualifications:

4+ years of ASIC verification experience, 1-2 years hands-on experience with UVM, Strong proficiency in SystemVerilog and UVM, Experience with complex ASICs or large FPGAs, Familiarity with IP block verification.

Key responsabilities:

  • Contribute to ASIC verification efforts for telecom projects
  • Collaborate on IP design/verification and subsystem integration
  • Address complex ASIC and FPGA design challenges
  • Ensure high-quality verification processes
  • Engage in team-oriented work on existing projects
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RDT ENGINEERS Large https://www.rdtengineers.com/
1001 - 5000 Employees
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Job description

Are you a ASIC Verifier looking for your next job adventure?


We are currently looking for a ASIC verifier to help our customer in the telecom sector. You will be involved in new and existing ASIC projects working in teams. The team is currently working on a mix of IP design/verification and different level of SubSys integration/verification.


Location: Remote (with occasional travel to Sweden).


Key Responsibilities:


  • Contribute to ASIC verification efforts for telecom-related projects.
  • Collaborate within a diverse team on IP design/verification and subsystem integration/verification.
  • Tackle complex ASIC and/or large FPGA design challenges, ensuring high-quality verification processes.

Passionate about Engineering - RDT Engineers


At RDT Engineers, our primary focus is our PEOPLE. We support our employees in professional and individual development. With our flat hierarchy, commitment and values, which inspire them to do their best. We pursue our PEOPLE’s work satisfaction and can guarantee highest quality, which leads to our second mission – our CLIENTS. We, our PEOPLE, provide engineering solutions that enable our customers to have a competitive advantage in efficiency, flexibility and costs.


Thanks to our PEOPLE, we have supplied the best engineering services since 2007 and offer the best and most flexible terms in the market for engineering services.



REQUISITOS MÍNIMOS:


Required Skills and Experience:


  • 4+ years of ASIC verification experience.
  • At least 1-2 years of hands-on experience with UVM (Universal Verification Methodology).
  • Strong proficiency in SystemVerilog and UVM for ASIC verification.
  • Proven experience working with complex ASICs and/or large FPGA designs.
  • Familiarity with IP block verification and multi-clock domain designs.
  • Excellent communication skills in English (both spoken and written).

Preferred Qualifications:


  • Experience with test bench structuring and design.
  • Leadership qualities and the ability to guide team members.
  • Knowledge of RTL design and scripting (e.g., Python, Perl, etc.).
  • Lab experience and familiarity with verification in a real-world environment.
  • Background in telecommunication.

Our purpose is to help engineers enjoy engineering. Join RDT Engineers.


Interested? APPLY NOW!


We encourage you to apply as soon as possible. Note that only your English CV is necessary.


#JoinRDT #enjoyengineering #rdtengineers

Required profile

Experience

Level of experience: Mid-level (2-5 years)
Spoken language(s):
EnglishEnglish
Check out the description to know which languages are mandatory.

Other Skills

  • Verbal Communication Skills
  • Problem Solving
  • Leadership

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