Offer summary
Qualifications:
4+ years of ASIC verification experience, 1-2 years hands-on experience with UVM, Strong proficiency in SystemVerilog and UVM, Experience with complex ASICs or large FPGAs, Familiarity with IP block verification.
Key responsabilities:
- Contribute to ASIC verification efforts for telecom projects
- Collaborate on IP design/verification and subsystem integration
- Address complex ASIC and FPGA design challenges
- Ensure high-quality verification processes
- Engage in team-oriented work on existing projects