Offer summary
Qualifications:
4+ years in ASIC verification, 2 years experience with UVM, Knowledge of SystemVerilog and UVM, Experience with complex ASIC/FPGA designs, Good English skills, speaking and writing.Key responsabilities:
- Support new and existing ASIC projects
- Work on IP design and verification
- Engage in SubSys integration/verification
- Collaborate with teams on projects
- Assist in test bench structuring and design