Offer summary
Qualifications:
BS or MS in Electrical Engineering or related field, 3-5 years of hardware design development experience, Expertise in Verilog, SystemVerilog, VHDL, SystemC, Experience with UVM environments and formal verification, Scripting and verification workflow skills.
Key responsabilities:
- Develop and customize hardware design platform
- Generate training data for enterprise LLMs
- Collaborate with research teams for actionable insights
- Ensure high standards in coding and documentation
- Identify needs to enhance LLM performance