Offer summary
Qualifications:
Bachelor's Degree in EE, CE or CS., 8+ years of relevant experience., Experience in RTL development (Verilog)., Understanding of ASIC design flow., Exposure to Digital systems and VLSI..Key responsabilities:
- Implement high-performance RTL designs.
- Analyze trade-offs for architectural decisions.
- Collaborate with cross-functional teams.
- Architect features for silicon debug.
- Develop IPs like GPU scheduler and DMA engines.