Offer summary

Qualifications:

Good DV skills with major GLS work experience., Expertise in testbench updates for GLS and scripting languages like Perl or Python., Experience with Make, Yaml, and Json file systems, as well as 0 delay simulations., Strong understanding of RTL synthesis, Static Timing Analysis, and LEC flows..

Key responsabilities:

Communicate requirements and issues with Implementation, PnR, and Design teams.

Perform flow optimizations using Grey/Black-boxing techniques.

Document processes and manage projects using Confluence, GIT, and JIRA.

Conduct post layout simulations with SDF back annotations for analysis.

Job description

Design Verification Engineer

Location : Remote

Semiconductor Industry

Good DV Skill with major GLS work experience.

Expertise in testbench updates for GLS

Expertise in Scripting languages perl or python

Experience with Make, Yaml & Json file systems.

Experience with 0 delay simulations and post layout simulations with SDF back annotations (Best/Typical/Worst Case analysis).

Good understanding of RTL synthesis , Static Timing Analysis & LEC Flows.

Experience with flow optimizations such as Grey/Black-boxing techniques

Good at communicating requirements/issues with Implementation, PnR and Design teams.

Working knowledge of Confluence documentation , version system GIT and Project execution with JIRA.

Please reply me with your updated resume and required details:

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Best Regards,

Salman Shaikh

9083410918

salman.s@eateam.com

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