Offer summary
Qualifications:
Bachelor's degree in Electrical/Computer Engineering, Minimum 3 years digital verification experience, Proficiency in SystemVerilog and/or VHDL, Strong understanding of UVM and OVM methodologies, Experience with industry-standard simulation tools.
Key responsabilities:
- Develop and execute verification plans for electronic designs
- Implement test-benches, test cases, and assertions
- Perform functional and performance verification of digital designs
- Debug design issues and maintain accurate documentation
- Enhance verification process and methodologies