Job description

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

Teradyne’s Semiconductor Test Division at our Agoura Hills, CA facility is looking for a summer 2025 intern to partner with our engineers and participate in the design of high-speed (> 1 Gbps) ICs and/or high-power, high-voltage ICs for ATE (Automatic Test Equipment) instruments.

As part of this team, they will assist design engineers in developing specifications, designing, simulating and characterizing analog circuits. You will be a key in assisting design engineers to optimize and characterize a circuit via simulation (with Cadence EDA tools) over all process and operating conditions.

Additionally, the selected intern may take part in the physical implementation (layout) of circuits, participate in documentation, plus be part of the design review as well as participate in IC evaluation in the lab.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

The right person for this role should be currently working on or planning on MSEE or PhD degree with emphases in mixed-signal and analog integrated circuit design.
Analog and/or Mixed-Signal integrated circuit design knowledge
Familiarity with Cadence EDA tools, Spectre and/or Hspice
Programming and Scripting, Matlab, C/C++, VBA, Python, Perl, SKILL etc
Knowledge working with lab equipment - oscilloscopes, DMM, etc.
Excellent written and verbal communication skills
Detail-oriented and possess excellent follow-up skills
Ability to manage own work with minimal direction
Must be available for entire duration of the Summer 2025 break
Must be able to work on-site at our Agoura Hills, CA facility on as-needed basis. Teradyne has a hybrid work-site model.

NICE To Have

Previous industry experience or academic experience with several design tapeouts is a plus
Design and/or layout experience in advanced FinFET processes (TSMC 16FFC or smaller)
Experience in high-speed CML logic design or CMOS logic design
Experience with power electronics
Experience with linear circuits
Verilog-a knowledge is plus

We are only considering candidates local to position location and are unable to provide relocation for this position.

Required profile